Semiconductor chips are typically connected to a printed circuit board that, in turn, interconnects the chips to the rest of circuitry with which the chips will operate, including other chips on the printed circuit board. In the past, the chips were spread out across the printed circuit board on their large flat sides in a simple two dimensional array. Over the years, the trend in the computer industry has been towards more densely packed printed circuit boards. Among the causes for this are the increasing demand for larger random access computer memories, faster computers, more compact computers, and a push to decrease costs of printed circuit boards by increasing the circuit density on the printed circuit board. In the mid-to-late 1980s, the industry switched over from a technology that attached computer chips to a printed circuit board through holes in the printed circuit board to one that used surface mounting technology. With the advent of surface mount technology, conventional through-holes on printed circuit boards have been replaced with conductive mounting pads on the surface of the printed circuit board. This allows for multiple layered circuit boards with a complex network of interconnect lines running between the layers of the board. In turn, this has allowed for the increase in the density of chips on a printed circuit board that not only decreases the size of the board, but also increases the operating speed of the computer by reducing the distance signals have to travel between chips on the board.
The move to surface mount technology has consequently resulted in the practice of positioning chips on a printed circuit board in a variety of configurations to increase chip density on the circuit board, and thereby decrease the distance between the chips to speed up operation of the overall system. Generally, conventional configurations stack the chips on one another to increase density. The practice of stacking the chips on one another is particularly adaptable to memory chips given the redundancies in their circuits. Up until the present, in order for the chips to be stacked on one another to increase chip density and achieve a three dimensional array on a circuit board, computer makers had to send chips to a third-party manufacturer that specialized in the technique of permanently bonding chips in a stacked fashion. Stacking the chips generally consisted of soldering them together. This, in turn, created a variety of problems including time delays inherent in having to rely on an outside manufacturing facility, and potential damage to the chip as a result of directly soldering the chips together.
Recent developments, in particular, those of the applicant of the present invention have resulted in new and much more efficient means for stacking chips on a printed circuit board in a three dimensional array. These developments are described in detail in U.S. Patents owned by the applicant herein, namely: U.S. Pat. No. 6,313,998 for a “Circuit Board Assembly Having a Three-Dimensional Array of Integrated Circuit Packages,” filed Apr. 2, 1999, and U.S. Pat. No. 6,487,078 for an “Electronic Module Having a Three-Dimensional Array of Carrier-Mounted Integrated Circuit Packages,” filed Mar. 13, 2000. Both of these U.S. Patents are incorporated herein by reference in their entirety and made part hereof as if set forth herein at length. The two referenced U.S. Patents describe a unique electronic module that, in effect, provides a platform that is placed over a chip on a circuit board and connects to contact pads on the circuit board that the platform shares with the chip underneath it. The second chip is then connected to the top of the platform to achieve a stacked three-dimensional array, as more fully described in the above referenced U.S. Patents. One variation of a chip carrier described and claimed in the above referenced U.S. Patents and is depicted in FIG. 1. There are a variety of chip carrier styles and designs. These styles and designs may be fabricated with a number of techniques. For example a chip carrier may be configured as a printed circuit board as shown in FIG. 4 of U.S. patent application Ser. No. 10/371,061. As another example, a chip carrier may be molded from a packaging process as depicted in FIG. 21B of U.S. patent application Ser. No. 10/371,061.
To maximize the advantages of the electronic chip carrying modules, the present invention provides, for example, a manufacturing process and apparatus that may automate and optimize their installation. Additionally, it should, for example, preferably be a manufacturing process and apparatus that may be used in-house by a surface mount assembly, computer or circuit board manufacturer without the need to use the services of a third-party manufacturer.